Design of 4 Bit Adder using 4 Full Adder

Hello Everyone, Today i am going to write the VHDL code for the 4 bit full adder. The VHDL code for the full adder is pretty simple and easy but when you have to write the VHDL Code for 4bit full adder you have to apply some logic.

To write the VHDL code for the following 4-bit full adder, you have to use the term PORT MAP.

VHDL Code for 4-bit full adder

Now, the code is:

library IEEE;
use IEEE.STD_LOGIC_1164.all;
ENTITY adder_4bit IS
         PORT(
         A:IN STD_LOGIC_VECTOR(3 down to 0);
         B:IN STD_LOGIC_VECTOR(3 down to 0);
         Carry:OUT STD_LOGIC;
         Sum:OUT STD_LOGIC_VECTOR(3 down to 0)
);
END ENTITY adder_4bit
ARCHITECTURE adder_4bit_structure OF adder_4bit IS

       COMPONENT fa IS
       PORT(A:IN STD_LOGIC;
                   B:IN STD_LOGIC;
                   C:IN STD_LOGIC;
                   Sum:OUT STD_LOGIC;
                   Carry:OUT STD_LOGIC;
                   );

END COMPONENT
SIGNAL s:STD_LOGIC_VECTOR(2 down to 0);
begin
               one:    fa PORT MAP(A(0), B(0), '0', sum(0), s(0));
               two:   fa PORT MAP(A(1), B(1), s(0), sum(1), s(1));
               three: fa PORT MAP(A(2), B(2), s(1), sum(2), s(2));
               four:  fa PORT MAP(A(3), B(3), s(2), sum(3), carry);
END ARCHITECTURE adder_4bit_structure